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ISL59534
Data Sheet August 29, 2007 FN6249.6
32x16 Video Crosspoint
The ISL59534 is a 300MHz 32x16 Video Crosspoint Switch. Each input has an integrated DC-restore clamp and an input buffer. Each output has a fast On-Screen Display (OSD) switch (for inserting graphics or other video) and an output buffer. The switch is non-blocking, so any combination of inputs to outputs can be chosen, including one channel driving multiple outputs. The Broadcast Mode directs one input to all 16 outputs. The output buffers can be individually controlled through the SPI interface, the gain can be programmed to +1 or +2, and each output can be placed into a high impedance mode. The ISL59534 offers a typical -3dB signal bandwidth of 300MHz. Differential gain of 0.025% and differential gain of 0.05, along with 0.1dB flatness out to 50MHz, make the ISL59534 suitable for many video applications. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible three-wire serial interface. The ISL59534 interface is designed to facilitate both fast updates and initialization. On power-up, all outputs are high impedance to avoid output conflicts. The ISL59534 is available in a 356 ball BGA package and specified over an extended -40C to +85C temperature range. The single-supply ISL59534 can accommodate input signals from 0V to 3.5V and output voltages from 0V to 3.8V. Each input includes a clamp circuit that restores the input level to an externally applied reference in AC-coupled applications. The ISL59535 is a fully differential input version of this device.
Features
* 32x16 non-blocking switch with buffered inputs and outputs * 300MHz typical bandwidth * 0.025%/0.05 dG/dP * Output gain switchable x1 or x2 for each channel * Individual outputs can be put in a high impedance state * -90dB Isolation at 6MHz * SPI digital interface * Single +5V supply operation * Pb-free available (RoHS compliant)
Applications
* Security camera switching * RGB routing * HDTV routing
Ordering Information
PART NUMBER (Note) ISL59534IKEZ TAPE & REEL PACKAGE (Pb-Free) 356 Ld BGA PKG. DWG. # V356.27x27A
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Block Diagram
VS VOVERn 16 OVERLAY VIDEO INPUTS OVERn 16 OVERLAY CHANNEL ENABLES
VREF
CLAMP 32 VIDEO INPUTS IN0 - IN31 32x16 SWITCH MATRIX 16 VIDEO OUTPUTS OUT0 - OUT15
CLAMP SDI SCLK SLATCH CLAMP ENABLE AV X1, X2 OUTPUT ENABLE
SPI INTERFACE AND CONTROL REGISTERS
VSDO SDO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006, 2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59534 Pinout
ISL59534 (356 LD BGA) TOP VIEW
A
In24 In25 In26 In27 In28 In29 In30 In31 Over15 Over14 Out13 Out12
B
Out15 Out14 Over13 Over12
C
In23 Vover15 Vover14 Vover13 Vover12
D
In22
VSDO
Vs Vs Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs
Vs Vs
Vover11 Out11
Over11
E
In21
F
In20
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs
Vover10 Out10 Over10
G
In19 SDO
Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs Vs
NC
H
In18 RESET Vover9 Over9 Out9
J
In17 SLATCH
K
In16 SCLK Vover8 Over8 Out8
L
In15 SDI
M
In14 VREF Vover7 Out7 Over7
N
In13
P
In12 Vover6 Out6 Over6
R
In11
T
In10 Vover5 Over5 Out5
U
In9
Vs
NC
Vs
Vs
Vs
NC
Vs
Vover0
Vs
Vs
Vover1
Vs
Vs
Vover2
Vs
Vs
Vover3
Vs
Vover4 Over4 Out4
V
In8
W
Over0 Over1 Out2 Out3
Y
In7 In6 In5 In4 In3 In2 In1 In0 Out0 Out1 Over2 Over3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
= NO BALLS BALLS LABELLED "NC" SHOULD BE LEFT UNCONNECTED - DO NOT TIE THEM TO GROUND! BALLS WITH NO LABELS MAY BE TIED TO GROUND TO SLIGHTLY REDUCE THERMAL IMPEDANCE.
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FN6249.6 August 29, 2007
ISL59534
Absolute Maximum Ratings (TA = +25C) Thermal Information
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . . 6.0V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA Maximum power supply (VS) slew rate . . . . . . . . . . . . . . . . . . 1V/s
Operating Conditions
ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
DC Electrical Specifications
PARAMETER VS VSDO AV GM
VS = 5V, RL = 150 unless otherwise noted. CONDITION MIN (Note 1) 4.5 Establishes serial data output high level AV = 1 AV = 2 AV = 1 AV = 2 AV = 1 AV = 2 Clamp function disabled (DC coupled inputs) Clamp function enabled, VIN = VREF + 0.5V 1.2 0.98 1.96 -1.5 -1.5 0 0.1 -10 0.5 -5 2 -110 -20 -100 60 24 50 385 280 1.2 8 -24 108 31 70 445 320 1.8 505 360 2.4 35 40 1 2 TYP MAX (Note 1) 5.5 5.5 1.02 2.04 +1.5 +1.5 3.5 3.8 1 10 UNIT V V V/V V/V % % V V A A A mV mV mA mA dB mA mA mA
DESCRIPTION Power Supply Voltage Power Supply for SDO output pin Gain (between all primary inputs and all overlay inputs) Gain Matching (to average of all other outputs) Video Input Voltage Range Video Output Voltage Range Input Bias Current
VIN VOUT IB IREF VOS IOUT PSRR IS
VREF Input Current Output Offset Voltage
Clamp function enabled AV = 1 AV = 2 Sourcing, RL = 10 to GND Sinking, RL = 10 to 2.5V AV = 2 Enabled, all outputs enabled, no load current Enabled, all outputs disabled, no load current Disabled
Output Current
Power Supply Rejection Ratio Supply Current
AC Electrical Specifications
PARAMETER BW -3dB BW 0.1dB SR TS Glitch Tover dG dP XTADJACENT XTHOSTILE VN NOTE:
VS = 5V, RL = 150 unless otherwise noted. CONDITION VOUT = 200mVP-P, AV = 2 VOUT = 200mVP-P, AV = 2 VOUT = 2VP-P, AV = 2 VOUT = 2VP-P, AV = 2 AV = 1 From OVER rising edge to output transition AV = 2, RL = 150 AV = 2, RL = 150 6MHz, AV = 1 6MHz, AV = 1 300 MIN (Note 1) TYP 300 50 520 12 40 6 0.025 0.05 -90 -72 18 740 MAX (Note 1) UNIT MHz MHz V/s ns mV ns %
DESCRIPTION 3dB Bandwidth 0.1dB Bandwidth Slew Rate Settling Time to 0.1% Switching Glitch, Peak Overlay Delay Time Diff Gain Diff Phase Adjacent Channel Crosstalk Hostile Crosstalk Input Referred Noise Voltage
dB dB nV/Hz
1. All Min/Max parameters are guaranteed by 100% production testing at TA = +25C. Typical values are for information purposes only.
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FN6249.6 August 29, 2007
ISL59534 Pin Descriptions
NAME IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 IN17 IN18 IN19 IN20 IN21 IN22 IN23 IN24 IN25 IN26 IN27 IN28 IN29 IN30 IN31 OUT0 OUT1 OUT2 OUT3 OUT4 NUMBER Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 V1 U1 T1 R1 P1 N1 M1 L1 K1 J1 H1 G1 F1 E1 D1 C1 A1 A2 A3 A4 A5 A6 A7 A8 Y10 Y12 W14 W16 V20 DESCRIPTION Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Input Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output
Pin Descriptions (Continued)
NAME OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OVER0 OVER1 OVER2 OVER3 OVER4 OVER5 OVER6 OVER7 OVER8 OVER9 OVER10 OVER11 OVER12 OVER13 OVER14 OVER15 VOVER0 VOVER1 VOVER2 VOVER3 VOVER4 VOVER5 VOVER6 VOVER7 VOVER8 VOVER9 NUMBER T20 P19 M19 K20 H20 F19 D19 A17 A15 B13 B11 W10 W12 Y14 Y16 V19 T19 P20 M20 K19 H19 F20 D20 B17 B15 A13 A11 V10 V12 V14 V16 V18 T18 P18 M18 K18 H18 DESCRIPTION Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Crosspoint Video Output Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Logic Control (with pulldown) Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input
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FN6249.6 August 29, 2007
ISL59534 Pin Descriptions (Continued)
NAME VOVER10 VOVER11 VOVER12 VOVER13 VOVER14 VOVER15 VREF NUMBER F18 D18 C17 C15 C13 C11 M3 DESCRIPTION Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input Overlay Video Input DC-restore clamp reference input. In an AC-coupled configuration (DC-Restore clamp enabled), the sync tip of composite video inputs will be restored to this level. Set to 0.3 to 0.7V for optimum performance. In an DC-coupled configuration (DC-Restore clamp disabled), this pin should be tied to ground. Do not let the VREF pin float! A floating VREF pin drifts high and, if the clamp function is enabled, will cause all of the outputs to simultaneously try to drive ~4V DC into their 150 loads. SLATCH J3 Serial Latch. Serial data is latched into ISL59534 on rising edge of SLATCH. SCLK SDI SDO K3 L3 G3 Serial data clock Serial data input Serial data output. Can be tied to SDI of another ISL59534 to enable daisy-chaining of multiple devices. RESET H3 Reset input. Pull high then low to reset device, but not needed in normal operation. Tie to ground in final application. Power supply for SDO pin. Tie to +5V for a 0 to 5V SDO output signal swing. VS GND NC +5V power supply Ground No Connect - Do not electrically connect to anything, including ground.
VSDO
D3
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves
MUX MODE AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0 33pF 27pF 22pF 15pF 10pF MUX MODE AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0 33pF 27pF 22pF 15pF
4.7pF 1pF
10pF 4.7pF 1pF
FIGURE 1. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, MUX MODE
FIGURE 2. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, MUX MODE
100 150
100 150
500 500 1.07k MUX MODE AV = 1 CL = 1pF INPUT_CH 0 OUTPUT_CH 0 MUX MODE AV = 2 CL = 1pF INPUT_CH 0 OUTPUT_CH 0 1.07k
FIGURE 3. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, MUX MODE
FIGURE 4. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, MUX MODE
OVERLAY MODE AV = 1 RL = 100 CL = 1pF INPUT_CH 31 OUTPUT_CH 31
OVERLAY MODE AV = 2 RL = 100 CL = 1pF INPUT_CH 31 OUTPUT_CH 31
FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 1
FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT, AV = 2
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves (Continued)
BROADCAST MODE AV = 1 RL = 100 INPUT_CH 0 OUTPUT_CH 0 33pF 27pF 22pF 15pF BROADCAST MODE AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0 33pF 27pF 22pF 15pF
10pF 4.7pF 1pF
10pF 4.7pF 1pF
FIGURE 7. FREQUENCY RESPONSE - VARIOUS CL, AV = 1, BROADCAST MODE
FIGURE 8. FREQUENCY RESPONSE - VARIOUS CL, AV = 2, BROADCAST MODE
100 100 150
503 1.07k BROADCAST MODE AV = 1 CL = 1pF INPUT_CH 0 OUTPUT_CH 0 1.07k BROADCAST MODE AV = 2 CL = 1pF INPUT_CH 0 OUTPUT_CH 0
FIGURE 9A. FREQUENCY RESPONSE - VARIOUS RL, AV = 1, BROADCAST MODE
FIGURE 10. FREQUENCY RESPONSE - VARIOUS RL, AV = 2, BROADCAST MODE
-30 -40 CROSSTALK (dB) -50 -60 -70 -80 -90 -100 1 10 100 ADJACENT IN CH14 OUT CH15 AV = 1 RL = 100 CL = 1pF ALL HOSTILE IN_CH14 BROADCAST TO ALL EXCEPT OUT_CH15
-30 -35 -40 ISOLATION (dB) -45 -50 -55 -60 -65 -70 -75 1k -80 1M ADJACENT IN CH14 OUT CH15 10M 100M FREQUENCY (Hz) 1G AV = 2 RL = 100 CL = 1pF ALL HOSTILE IN_CH14 BROADCAST TO ALL EXCEPT OUT_CH15
FREQUENCY (MHz)
FIGURE 11. CROSSTALK - AV = 1
FIGURE 12. CROSSTALK - AV = 2
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves (Continued)
AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0 VOP-P = 2V THD 2nd HD AV = 2 RL = 100 INPUT_CH 0 OUTPUT_CH 0 FREQUENCY = 1MHz
THD 2nd HD
3rd HD 3rd HD
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs VOUT_P-P
FIGURE 15. DISABLED OUTPUT IMPEDANCE
FIGURE 16. ENABLED OUTPUT IMPEDANCE
MUX MODE AV = 1 RL = 100 INPUT_CH 31 OUTPUT_CH 31 FALL TIME 2.65ns
RISE TIME 2.35ns
MUX MODE AV = 1 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 17. RISE TIME - AV = 1
FIGURE 18. FALL TIME - AV = 1
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves (Continued)
MUX MODE AV = 2 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FALL TIME 2.35ns
RISE TIME 2.19ns
MUX MODE AV = 2 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 19. RISE TIME - AV = 2
FIGURE 20. FALL TIME - AV = 2
MUX MODE AV = 1 RL = 100 INPUT_CH 31 OUTPUT_CH 31 SLEW RATE 448V/s SLEW RATE -436V/s
MUX MODE AV = 1 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 21. RISING SLEW RATE - AV = 1
FIGURE 22. FALLING SLEW RATE - AV = 1
MUX MODE AV = 2 RL = 100 INPUT_CH 31 OUTPUT_CH 31 SLEW RATE 531V/s
SLEW RATE -511V/s
MUX MODE AV = 2 RL = 100 INPUT_CH 31 OUTPUT_CH 31
FIGURE 23. RISING SLEW RATE - AV = 2
FIGURE 24. FALLING SLEW RATE - AV = 2
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves (Continued)
OUTPUT
OUTPUT
OVERLAY LOGIC INPUT
OVERLAY LOGIC INPUT
FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME
FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 27. DIFFERENTIAL GAIN, AV = 2
FIGURE 28. DIFFERENTIAL PHASE, AV = 2
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 29. DIFFERENTIAL GAIN, AV = 2
FIGURE 30. DIFFERENTIAL PHASE, AV = 2
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves (Continued)
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 31. DIFFERENTIAL GAIN, AV = 1
FIGURE 32. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 31 OUTPUT_CH 31 OSC = 40mV
FIGURE 33. DIFFERENTIAL GAIN, AV = 1
FIGURE 34. DIFFERENTIAL GAIN, AV = 1
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 35. DIFFERENTIAL GAIN, AV = 2
FIGURE 36. DIFFERENTIAL PHASE, AV = 2
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves (Continued)
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 37. DIFFERENTIAL GAIN, AV = 2
FIGURE 38. DIFFERENTIAL PHASE, AV = 2
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 39. DIFFERENTIAL GAIN, AV = 1
FIGURE 40. DIFFERENTIAL PHASE, AV = 1
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 31 OSC = 40mV
FIGURE 41. DIFFERENTIAL GAIN, AV = 1
FIGURE 42. DIFFERENTIAL PHASE, AV = 1
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FN6249.6 August 29, 2007
ISL59534 Typical Performance Curves (Continued)
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
AV = 2 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, AV = 2
FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, AV = 2
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
AV = 1 RL = 150 INPUT_CH 00 OUTPUT_CH 00 OSC = 40mV
FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, AV = 1
FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, AV = 1
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FN6249.6 August 29, 2007
3dB Bandwidth, MUX Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 OUTPUT CHANNELS 5 6 7 8 9 10 11 12 13 14 15 238 199 230 238 220 280 287 269 196 281 285 282 265 265 273 262 217 277 288 269 274 255 268 278 286 277 288 350 216 285 281 274 283 274 256 258 272 271 267 290 272 1 2 3 4 5 270 6 7 8 9 10 268 11 12 13 14 15 235 16 17 18 19 20 236 21 22 23 24 25 235 214 26 27 28 29 30 31 236
OUTPUT CHANNELS
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FN6249.6 August 29, 2007
ISL59534
3dB Bandwidth, MUX Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 311 288 313 314 297 336 345 350 289 351 371 350 339 321 351 304 290 353 371 360 350 348 327 325 338 355 354 381 334 366 348 314 348 341 317 350 350 366 340 370 348 1 2 3 4 5 323 6 7 8 9 10 324 11 12 13 14 15 305 16 17 18 19 20 313 21 22 23 24 25 320 294 26 27 28 29 30 31 308
3dB Bandwidth, Broadcast Mode, AV = 1, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 OUTPUT CHANNELS 5 6 7 8 9 10 11 12 13 14 15 196 172 165 152 133 132 125 127 124 116 114 108 106 108 104 107 110 108 98 103 98 98 98 99 101 99 97 95 87 86 84 96 96 94 97 88 1 204 2 193 163 128 123 113 113 94 90 3 175 4 154 5 154 6 158 7 161 8 169 9 157 10 155 11 146 12 125 13 121 14 115 15 109 104 99 95 86 91 87 88 89 84 84 80 79 81 78 81 113 112 112 114 126 126 128 129 124 118 114 111 88 87 98 100 99 98 105 120 122 129 85 81 88 82 81 79 16 81 17 81 18 79 19 80 20 85 21 85 22 86 23 86 24 83 25 82 26 82 27 77 28 80 29 82 85 30 85 31 86 87 89 89 89 92 92 97 100 100 102 102 106 114 115 131
OUTPUT CHANNELS
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FN6249.6 August 29, 2007
ISL59534
3dB Bandwidth, Broadcast Mode, AV = 2, RL = 100 [MHz]
INPUT CHANNELS 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 270 240 233 204 172 170 152 155 146 133 129 119 116 120 113 117 121 118 106 112 105 105 106 108 110 107 104 101 93 91 88 103 103 102 106 94 1 277 2 268 223 158 146 128 126 103 96 3 247 4 213 5 216 6 227 7 244 8 258 9 223 10 208 11 196 12 147 13 142 14 132 15 123 112 108 105 92 97 93 94 93 90 89 84 83 84 82 85 130 127 127 130 153 150 158 163 149 140 133 126 94 93 106 107 107 108 113 140 146 161 89 89 94 85 88 83 16 85 17 85 18 85 19 86 20 91 21 91 22 92 23 93 24 90 25 88 26 86 27 85 28 89 29 90 88 30 92 31 94 92 95 95 94 98 99 105 109 109 113 112 117 135 133 164
ISL59534 Block Diagram
VS VOVERn OVERn 16 OVERLAY CHANNEL ENABLES
VREF
16 OVERLAY VIDEO INPUTS
CLAMP 32 VIDEO INPUTS IN0 - IN31 32x16 SWITCH MATRIX 16 VIDEO OUTPUTS OUT0 - OUT15
CLAMP SDI SCLK SLATCH CLAMP ENABLE AV X1, X2 OUTPUT ENABLE
SPI INTERFACE AND CONTROL REGISTERS
VSDO SDO
General Description
The ISL59534 is a 32x16 integrated video crosspoint switch matrix with input and output buffers and On-Screen Display (OSD) insertion. This device operates from a single +5V supply. Any output can be generated from any of the 32 input video signal sources, and each output can have OSD information inserted through a dedicated, fast 2:1 mux located before the output buffer. There is also a Broadcast mode allowing any one input to be broadcast to all 16 outputs. A DC restore clamp function enables the ISL59534 to AC-couple incoming video. The ISL59534 offers a -3dB signal bandwidth of 300MHz. Differential gain and differential phase of 0.025% and 0.05 respectively, along with 0.1dB flatness out to 50MHz make this ideal for multiplexing composite NTSC and PAL signals. The switch matrix configuration and output buffer gain are programmed through an SPI/QSPITM-compatible, three-wire serial interface. The ISL59534 interface is designed to facilitate both fast initialization and configuration changes. On power-up, all outputs are initialized to the disabled state to avoid output conflicts in the user's system.
Serial Interface
The ISL59534 is programmed through a simple serial interface. Data on the SDI (serial data input) pin is shifted into a 16-bit shift register on the rising edge of the SCLK (serial clock) signal. (This is continuously done regardless of the state of the SLATCH signal.) The LSB (bit 0) is loaded first and the MSB (bit 15) is loaded last (see the Serial Timing Diagram). After all 16 bits of data have been loaded into the shift register, the rising edge of SLATCH updates the internal registers. While the ISL59534 has an SDO (Serial Data Out) pin, it does not have a register readback feature. The data on the SDO pin is an exact replica of the incoming data on the SDI pin, delayed by 15.5 SCLKs (an input bit is latched on the rising edge of SLCK, and is output on SDO on the falling edge of SLCK 15.5 SCLKs later). Multiple ISL59534's can be daisy-chained by connecting the SDO of one to the SDI of the other, with SCLK and SLATCH common to all the daisychained parts. After all the serial data is transmitted (16 bits * n devices = 16*n SCLKs), the rising edge of SLATCH will update the configuration registers of all n devices simultaneously. The Serial Timing Diagram and Serial Timing Parameters table on page 17 show the timing requirements for the serial interface.
Digital Interface
The ISL59534 uses a serial interface to program the configuration registers. The serial interface uses three signals (SCLK, SDI, and SLATCH) for programming the ISL59534, while a fourth signal (SDO) enables optional daisy-chaining of multiple devices. The serial clock can run at up to 5MHz (5Mbits/s).
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FN6249.6 August 29, 2007
ISL59534 Serial Timing Diagram
SLATCH
SLATCH falling edge timing/placement is a "don't care." Serial data is latched only on rising edge of SLATCH. tSL
T
SCLK
tSD
tHD
tw
SDI
B0 (LSB) B0
(previous)
B1
B2
B15 (MSB) B15
(previous)
SDO
B1
(previous)
B2
(previous)
B0 (LSB)
B1
B2
SDO = SDI delayed by 15.5 SCLKs to allow daisy-chaining of multiple ISL59534s. SDO changes on the falling edge of SCLK.
TABLE 1. SERIAL TIMING PARAMETERS PARAMETER T tW tSD tHD tSL RECOMMENDED OPERATING RANGE 200ns 0.50 * T 20ns 20ns 20ns SCLK period Clock Pulse Width Data Setup Time Data Hold Time Final SLCK rising edge (latching B15) to SLATCH rising edge DESCRIPTION
Programming Model
The ISL59534 is configured by a series of 16-bit serial control words. The three MSBs (B15-13) of each serial word determine the basic command:
TABLE 2. COMMAND FORMAT B15 0 0 0 0 1 B14 0 0 1 1 1 B13 0 1 0 1 1 COMMAND INPUT/OUTPUT: Maps input channels to output channels OUTPUT ENABLE: Output enable for individual channels GAIN SET: Gain (+1 or +2) for each channel BROADCAST: Enables broadcast mode and selects the input channel to be broadcast to all output channels CONTROL: Clamp on/off, operational/standby mode, and global output enable/disable NUMBER OF WRITES 32 (1 channel per write) 4 (4 channels per write) 4 (4 channels per write) 1 1
Mapping Inputs to Outputs Inputs are mapped to their desired outputs using the input/output control word. Its format is:
TABLE 3. INPUT/OUTPUT WORD B15 0 B14 0 B13 0 B12 I4 B11 I3 B10 I2 B9 I1 B8 I0 B7 B6 B5 B4 O3 B3 O2 B2 O1 B1 O0 B0
I4:I0 form the 5-bit word indicating the input channel (0 to 31), and O3:O0 determine the output channel which that input channel will map to. One input can be mapped to one or multiple outputs. To fully program the ISL59534, 32 INPUT/OUTPUT words must be transmitted - one for each input channel. Note: Broadcast Mode must be disabled when configuring input/output mapping. INPUT/OUTPUT words transmitted while in Broadcast Mode will not be processed correctly and result in corrupt channel mapping when Broadcast Mode is disabled.
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Enabling Outputs The output enable control word is used to enable individual outputs. There are 16 channels to configure, so this is accomplished by writing 4 serial words, each controlling a bank of eight outputs at a time. The bank is selected by bits B9 and B8. The output enable control word format is:
TABLE 4. OUTPUT ENABLE FORMAT B15 B14 B13 B12 B11 B10 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 B9 0 0 1 1 B8 0 1 0 1 B7 B6 O3 O7 O11 O15 B5 B4 O2 O6 O10 O14 B3 B2 O1 O5 O9 O13 B1 B0 O0 O4 O8 O12
Setting the ON bit = 0 tri-states the output. Setting the ON bit = 1 enables the output if the Global Output Enable bit is also set (the individual output enable bits are ANDed with the Global Output Enable bit before they are sent to the output stage). Setting the Gain The gain of each output may be set to +1 or +2 using the Gain Set word. It is in the same format as the output enable control word:
TABLE 5. GAIN SET FORMAT B15 B14 B13 B12 B11 B10 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B9 0 0 1 1 B8 0 1 0 1 B7 B6 G3 G7 G11 G15 B5 B4 G2 G6 G10 G14 B3 B2 G1 G5 G9 G13 B1 B0 G0 G4 G8 G12
Set GN = 0 for a gain of +1 or 1 for a gain of +2. Broadcast Mode The Broadcast Mode routes one input to all 16 outputs. The broadcast control word is:
TABLE 6. BROADCAST FORMAT B15 0 B14 1 B13 1 B12 I4 B11 I3 B10 I2 B9 I1 B8 I0 B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 Enable Broadcast 0: Broadcast Mode Disabled 1: Broadcast Mode Enabled
I4:I0 form the 5 bit word indicating the input channel (0 to 31) to be sent to all 16 outputs. Set the Enable Broadcast bit (B0) = 1 to enable Broadcast Mode, or to 0 to disable Broadcast Mode. When Broadcast Mode is disabled, the previous channel assignments are restored. Control Word The ISL59534's power-on reset disables all outputs and places the part in a low-power standby mode. To enable the device, the following control word should be sent:
TABLE 7. CONTROL WORD FORMAT B15 B14 B13 B12 B11 B10 1 1 1 0 0 0 B9 B8 B7 B6 B5 B4 B3 B2 0 0 0 0 0 0 B1 B0
0 Clamp 0: Clamp Disabled 1: Clamp Enabled
Global Output Enable Power 0: All outputs tri-stated 0: Standby 1: Operational 1: Individual Output Enable bits control outputs
The Clamp bit enables the input clamp function, forcing the AC-coupled signal's most negative point to be equal to VREF. Note: The Clamp bit turns the DC-Restore clamp function on or off for all channels - there is no DC-Restore on/off control for individual channels. The DC-Restore function only works with signals with sync tips (composite video). Signals that do 18 not have sync tips (the Chroma/C signal in s-video and the Pb, Pr signals in Component video), will be severely distorted if run through a DC-Restore/clamp function.
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For this reason, the ISL59534 must be in DC-coupled mode (Clamp Disabled) to be compatible with s-video and component video signals.
Linear Operating Region
In addition to bandwidth optimization, to get the best linearity the ISL59534 should be configured to operate in its most linear operating region. Figure 48 shows the differential gain curve. The ISL59534 is a single supply 5V design with its most linear region between 0.1 and 2V. This range is fine for most video signals whose nominal signal amplitude is 1V. The most negative input level (the sync tip for composite video) should be maintained at 0.3V or above for best operation.
Bandwidth Considerations
Wide frequency response (high bandwidth) in a video system means better video resolution. Four sets of frequency response curves are shown in Figure 47. Depending on the switch configurations, and the routing (the path from the input to the output), bandwidth can vary between 100MHz and 350MHz. A short discussion of the trade-offs -- including matrix configuration, output buffer gain selection, channel selection, and loading -- follows.
2 MUX, AV = 2 NORMALIZED GAIN (dB) 0 -2 -4 -6 -8 -10 1 10 100 1000 FREQUENCY (MHz) BROADCAST, AV = 1 BROADCAST, AV = 2 MUX, AV = 1
FIGURE 48. DIFFERENTIAL GAIN RESPONSE
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES
In a DC-coupled application, it is the system designer's responsibility to ensure that the video signal is always in the optimum range. When AC coupling, the ISL59534's Clamp (also called "DC restore") function automatically and continuously adjusts the DC level so that the most negative portion of the video is always equal to VREF. A discussion of the benefits of the DC restoration function begins by understanding the Clamp circuit shown in Figure 49. The incoming video signal is typically terminated into 75, then AC coupled through C1, at which point it is connected to the base of the buffer's diff pair. These components form the video path. The Clamp function consists of Q1, D1, Q2, D2, the two current sources, and the 3 switches controlled by the Clamp Enable signal. The VREF voltage is level-shifted up two diode drops (Q1 and D1) to the base of Q2. If the voltage at the cathode of D2 goes below VREF, Q2 and D2 will turn on, keeping the INx voltage at VREF. If the voltage at INx is greater than VREF, Q2 and D2 are off and the INx node is high impedance. This is how the clamp function forces the lowest portion of the video signal (the sync tip) to always be equal to or greater than VREF. To make sure that the sync tip is always equal to (not equal to or greater than) VREF, i1 is constantly sinking ~2A of current from C1. This causes each sync tip to be slightly lower voltage than the previous sync tip, causing Q2 and D2 to turn on at each sync tip and raise the voltage to VREF. The 2A pulldown with a 0.1uF capacitor and a 15kHz HSYNC frequency results in 1.3mV of "droop" across every line, or
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In multiplexer mode, one input typically drives one output channel, while in broadcast mode, one input drives all 16 outputs. As the number of outputs driven increases, the parasitic loading on that input increases. Broadcast Mode is the worst-case, where the capacitance of all 16 channels loads one input, reducing the overall bandwidth. In addition, due to internal device compensation, an output buffer gain of +2 has higher bandwidth than a gain of +1. Therefore, the highest bandwidth configuration is multiplexer mode (with each input mapped to only one output) and an output buffer gain of +2. The relative locations of the input and output channels also have significant impact on the device bandwidth (due to the layout of the ISL59534 silicon). When the input and output channels are further away, there are additional parasitics as a result of the additional routing, resulting in lower bandwidth. The bandwidth does not change significantly with resistive loading as shown in the typical performance curves. However several of the curves demonstrate that frequency response is sensitive to capacitance loading. This is most significant when laying out the PCB. If the PCB trace length between the output of the crosspoint switch and the backtermination resistor is not minimized, the additional parasitic capacitance will result in some peaking and eventually a reduction in overall bandwidth.
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ISL59534
0.2% of the video signal. Because 1.3mV is only 0.2% of a 0.7V video signal, this droop is imperceptible to the human eye. delivering acceptable droop and CIN = 0.001F producing excessive droop. When the clamp function is disabled in the CONTROL register (Clamp = 0) to allow DC-coupled operation, the ICLAMP current sinks/sources are disabled and the input passes through the DC Restore block unaffected. In this application VREF may be tied to GND.
Overlay Operation
Q2 D1 ~0.4V D3 SS12 VIDEOIN C1 R1 75 VREF C2 (110A) 0.1F INx 0.1F INPUT TO BUFFER Q1 D2
The ISL59534 features an overlay feature, that allows an external video signal or DC level to be inserted in place of that output channel's video. When the OVERN signal is taken high, the output signal on the OUTN pin is replaced with the signal on the VOVERN pin. There are several ways the overlay feature can be used. Toggling the OVERN signal at the frame rate or slower will replace the video frame(s) on the OUTN pin with the video supplied on the VOVERN pin. Another option (for OSD displays, for example), is to put a DC level on the VOVERN line and toggle the OVERN signal at the pixel rate to create a monocolor image "overlaid" on channel N's output signal.
i1
CLAMP ENABLE
FIGURE 49. DC RESTORE BLOCK DIAGRAM
Finally, by enabling the OVERN signal for some portion of each line over a certain amount of lines, a picture-in-picture function can be constructed. It's important to note that the overlay inputs do not have the DC Restore function previously described - the overlay signal is DC coupled into the output. It is the system designer's responsibility to ensure that the video levels are in the ISL59534's linear region and matching the output channel's offset and amplitude. One easy way to do this is to run the video to be overlaid through one of the ISL59534's unused channels and then into the VOVERN input. The OVERN pins all have weak pulldowns, so if they are unused, they can either be left unconnected or tied to GND.
This is how the video is "DC-restored" after being AC coupled into the ISL59534. The sync tip voltage will be equal to VREF on the right side of C1, regardless of the DC level of the video on the left side of C1. Due to various sources of offset in the actual clamp function, the actual sync tip level is typically about 75mV higher than VREF (for VREF = 0.4V).
Power Dissipation and Thermal Resistance
With a large number of switches, it is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the crosspoint switch in a safe operating area. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
FIGURE 50. DC RESTORE VIDEO WAVEFORMS
It is important to choose the correct value for CIN. Too small a value will generate too much droop, and the image will be visibly darker on the right than on the left. A CIN value that is too large may cause the clamp to fail to converge. The droop rate (dV/dt) is i1/CIN volts/second. In general, the droop voltage should be limited to <1 IRE over a period of one line of video; so for 1 IRE = 7mV, IB = 10A maximum, and an NTSC waveform we will set CIN > 10A*60s/7mV = 0.086F. Figure 50 shows the result of CIN = 0.1F
(EQ. 1)
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Where: * TJMAX = Maximum junction temperature = +125C * TAMAX = Maximum ambient temperature = +85C * JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
n
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------R Li
V OUTi
(EQ. 2)
Where: * VS = Supply voltage = 5V * ISMAX = Maximum quiescent supply current = 505mA * VOUT = Maximum output voltage of the application = 2V * RLOAD = Load resistance tied to ground = 150 * n = 1 to 16 channels
n
PD MAX = V S x I SMAX +
i=1
( VS - VOUTi ) x ----------------- = R Li
V OUTi
3.2W (EQ. 3)
The required JA to dissipate 3.2W is:
T JMAX - T AMAX JA = -------------------------------------------- = 12.5 ( C/W ) PD MAX
(EQ. 4)
Table 8 shows JA thermal resistance results with a Wakefield heatsink and without heatsink and various airflow. At the thermal resistance equation shows, the required thermal resistance depends on the maximum ambient temperature.
TABLE 8. JA THERMAL RESISTANCE [C/W] Airflow [LFM] No Heatsink Wakefield 658-25AB Heatsink 0 18 16.0 250 14.3 7.0 500 13.0 6.0 750 12.6 4.7
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
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ISL59534
356 Lead HBGA Package
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